Statement
I am a dedicated EEE student at Imperial College London with a relentless drive for building and understanding complex hardware systems. My approach is defined by self-directed study and a proven ability to perform in high-stakes technical environments, evidenced by a 6th place finish at the Citadel Datathon 2025. I am focused on bridging the gap between hardware fundamentals and modern signal processing, and I am actively seeking a 2026 Summer Internship where I can apply a high-output work ethic to real-world engineering challenges.
Work & Projects
F1 FPGA Sequence
A hardware-based reaction timer implementing the FIA start sequence. Developed in SystemVerilog to ensure millisecond precision and zero-latency logic.
Project Joker
An AI-powered synthesis engine that leverages Gemini LLMs to transform dense academic materials into structured digital flashcards.
Proficiencies
Technical: SystemVerilog, Python (Django), MATLAB, C++.
Theory: Signal Theory, Embedded Systems, Analog & Digital Circuit Design, and Philosophy of Logic. Active curiosity in Quantum Computing.
Personal: Competing in local Padel tournaments and casual Chess.